SAN FRANCISCO–While the transistor may be on the minds of many a process R&D engineer these days, back-end-of-line (BEOL) interconnect technology and the materials challenges there– namely integrating ...
Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower ...
The shift from planar SoCs to 3D-ICs and advanced packages requires much thinner wafers in order to improve performance and reduce power, reducing the distance that signals need to travel and the ...
Power consumption is a crucial consideration for all types of electronics. As critical power components used in a wide range of electronic products, power MOSFET and other types of power semiconductor ...
The Soitec Group and the SEZ Group have initiated a joint development program (JDP) intended to speed the industrialisation of next-generation strained silicon-on-insulator (sSOI) substrates. Under ...
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