TechRepublic

Low Power VLSI CMOS Design by DCG Technique

The demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power efficient design techniques has grown ...
Electronics Weekly

VLSI Symposium: 7bit 150Gsample/s DAC on 5nm CMOS

Imec built a 7bit 150Gsample/s digital to analogue converter using 5nm finfet CMOS. Revealed at the Symposium on VLSI Technology and Circuits in Kyoto, it achieves data rates of up to 300 Gbit/s using ...
Design-Reuse

Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology

The Bandgap Reference (BGR) circuit is a key element in Very-large-scale Integration (VLSI) designs, providing a stable reference voltage that is crucial for the performance and reliability of analog ...
Electronic Design

Layout-Dependent Modeling Boosts CMOS Gate Density

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...
TechRepublic

Low Power State Retention Technique for CMOS VLSI Design

Mobile computing and mobile communication applications which are powered by battery, the battery life is a major concern. Leakage power dissipation is critical in VLSI circuits as the battery leaks ...