Semiconductor Engineering

How To Close Timing With An eFPGA Hosted In An SoC

eFPGAs are embeddable IP that include look-up tables, memories, and DSP building blocks, allowing designers to add a programmable logic fabric to their SoC. The Speedcore IP can be configured to any ...
EDN

Verifying timing of external IP key to SoC success

External intellectual property spans a broad range of technology. It can be as complex as an embedded digital signal processing (DSP) core or as primitive as a RAM instance. IP can come from an ...
EDN

Simplifying SoC IO timing closure

Modern day SoCs are getting complex with every passing day. In order to provide user multiple connectivity options, designers are stuffing SoC with multiple IO protocols. There are several factors ...
Design-Reuse

FPGA prototyping of complex SoCs: Partitioning and Timing Closure Challenges with Solutions

In the nanometer era, complex SoCs have higher risk of re-spins. Undoubtedly FPGA prototyping is the right way of pre-silicon SoC validation, accelerate system software development and to meet time-to ...
Semiconductor Engineering

How To Reduce Timing Closure Headaches

As chips have become more complex, timing closure has provided some of the most vexing challenges facing design engineers today. This step requires an increasing amount of time to complete and adds ...
Design-Reuse

IP Verification : Verifying timing of external IP key to SoC success

External intellectual property spans a broad range of technology. It can be as complex as an embedded digital signal processing (DSP) core or as primitive as a RAM instance. IP can come from an ...