EDN

Toshiba cuts capacitor from DRAM cell design

TOKYO — Toshiba Corp. has developed a one-transistor, no-capacitor cell structure that it claims solves the difficulties encountered in producing DRAMs in sub-0.1-micron process technology. The ...
EDN

Renesas memory cell mixes SRAM, DRAM tech

Tokyo – Renesas Technology Corp. has developed a new SRAM memory cell structure that combines SRAM and DRAM technologies. The device is about half the size of a conventional SRAM cell, but still has ...
Electronic Design

SOI Drops The Capacitor, Doubles Embedded DRAM Density

Implemented in a standard 90-nm SOI process, the memory cell can be as small as 0.1 µm 2. That's about one-tenth the size of the smallest SRAM cells and less than half the size of most DRAM cells.
Embedded

Happy birthday DRAM!

On June 4, 1968, Robert Dennard was granted a patent for a single transistor, single capacitor DRAM cell design idea. This doesn’t sound earth-shattering today, but back in the sixties, this was a ...
Hosted on MSN

3D X-DRAM aims for 10x capacity of today's memory — NEO Semiconductor's memory has up to 512 Gb per module

NEO Semiconductor is once again announcing a new technology that hopes to revolutionize the state of DRAM memory. Today, the company unveiled two new 3D X-DRAM cell designs, 1T1C and 3T0C. The ...
Digi Times

DRAM process development challenges: DRAM structure in process miniaturization

Since its 1970 debut, DRAM has supplanted magnetic core memory as an essential element in von Neumann's computer architecture. By the mid-1980s, fueled by the popularity of PCs and workstations, DRAM ...
Semiconductor Engineering

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of ...
Semiconductor Engineering

Manufacturing Bits: Dec. 15

At the recent IEEE International Electron Devices Meeting (IEDM) in Washington, D.C., chipmakers presented papers on several technologies, including one unlikely topic—DRAM scaling. For years, it was ...
sciencex

Imec Demonstrates Capacitor-less IGZO-Based DRAM Cell With >400s Retention Time

This week, at the 2020 International Electron Devices Meeting, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a novel dynamic random-access ...
Business Wire

Samsung Starts Mass Producing Industry’s First 10-Nanometer Class DRAM

SEOUL, South Korea--(BUSINESS WIRE)--Samsung Electronics Co., Ltd., the world leader in advanced memory technology, announced today that it has begun mass producing the industry’s first 10-nanometer ...
TechSpot

Neo Semiconductor launches 3D X-DRAM, world-first technology for 3D DRAM memory chips

What just happened? A Californian company is launching what it calls a ground-breaking solution for increasing DRAM chip density with 3D stacking technology. The new memory chips will greatly improve ...